SEMC_PODF=SEMC_PODF_0, PERIPH_CLK_SEL=PERIPH_CLK_SEL_0, AHB_PODF=AHB_PODF_0, IPG_PODF=IPG_PODF_0, SEMC_ALT_CLK_SEL=SEMC_ALT_CLK_SEL_0, PERIPH_CLK2_PODF=PERIPH_CLK2_PODF_0, SEMC_CLK_SEL=SEMC_CLK_SEL_0
CCM Bus Clock Divider Register
| SEMC_CLK_SEL | SEMC clock source select 0 (SEMC_CLK_SEL_0): Periph_clk output will be used as SEMC clock root 1 (SEMC_CLK_SEL_1): SEMC alternative clock will be used as SEMC clock root |
| SEMC_ALT_CLK_SEL | SEMC alternative clock select 0 (SEMC_ALT_CLK_SEL_0): PLL2 PFD2 will be selected as alternative clock for SEMC root clock 1 (SEMC_ALT_CLK_SEL_1): PLL3 PFD1 will be selected as alternative clock for SEMC root clock |
| IPG_PODF | Divider for ipg podf. 0 (IPG_PODF_0): divide by 1 1 (IPG_PODF_1): divide by 2 2 (IPG_PODF_2): divide by 3 3 (IPG_PODF_3): divide by 4 |
| AHB_PODF | Divider for AHB PODF 0 (AHB_PODF_0): divide by 1 1 (AHB_PODF_1): divide by 2 2 (AHB_PODF_2): divide by 3 3 (AHB_PODF_3): divide by 4 4 (AHB_PODF_4): divide by 5 5 (AHB_PODF_5): divide by 6 6 (AHB_PODF_6): divide by 7 7 (AHB_PODF_7): divide by 8 |
| SEMC_PODF | Post divider for SEMC clock 0 (SEMC_PODF_0): divide by 1 1 (SEMC_PODF_1): divide by 2 2 (SEMC_PODF_2): divide by 3 3 (SEMC_PODF_3): divide by 4 4 (SEMC_PODF_4): divide by 5 5 (SEMC_PODF_5): divide by 6 6 (SEMC_PODF_6): divide by 7 7 (SEMC_PODF_7): divide by 8 |
| PERIPH_CLK_SEL | Selector for peripheral main clock 0 (PERIPH_CLK_SEL_0): derive clock from pre_periph_clk_sel 1 (PERIPH_CLK_SEL_1): derive clock from periph_clk2_clk_divided |
| PERIPH_CLK2_PODF | Divider for periph_clk2_podf. 0 (PERIPH_CLK2_PODF_0): divide by 1 1 (PERIPH_CLK2_PODF_1): divide by 2 2 (PERIPH_CLK2_PODF_2): divide by 3 3 (PERIPH_CLK2_PODF_3): divide by 4 4 (PERIPH_CLK2_PODF_4): divide by 5 5 (PERIPH_CLK2_PODF_5): divide by 6 6 (PERIPH_CLK2_PODF_6): divide by 7 7 (PERIPH_CLK2_PODF_7): divide by 8 |